Split-gate flash technology has been widely employed in medium-low density applications. As shown in FIG. 1A, an example of such a structure includes a substrate 101 with source/drain regions 103, a word gate (WG) 105 (over a gate dielectric layer 107), a control gate (CG) 109 on a interpoly dielectric (IPD) layer 111 over a floating gate (FG) 113 and a tunneling oxide (TO) layer 115, and a spacer 117. As another example, FIG. 1B illustrates a structure including the substrate 101 with the source/drain regions 103, the word gate 105 (over the gate dielectric layer 107), the control gate 109 on the interpoly dielectric layer 111 over the floating gate 113 and the tunneling oxide layer 115, and the spacer 117. The structure shown in FIG. 1B also includes an erase gate (EG) 119. As illustrated in FIG. 1A and 1B, source-side injection (SSI) may be employed to program the exemplary structures (e.g., programming represented by black arrows). As illustrated in FIG. 1A and 1B, a Fowler-Nordheim (FN) erase may be accomplished through the control gate 109 (e.g., white arrow in FIG. 1A) or through the erase gate 119 (e.g., white arrow in FIG. 1B) to remove the charges.
Conventional split-gate flash memory structures are problematic in various respects, such as read disturbance, program disturbance, and sidewall scaling limitations. For example, the structures illustrated in FIGS. 2A and 2B are similar to that shown in FIG. 1A, and comprise a substrate 201 with source/drain regions 203, a word gate 205 (over a gate dielectric 207), a control gate 209 on a interpoly dielectric layer 211 over a floating gate 213 and a tunneling oxide layer 215, and a spacer 217. In FIG. 2A, charge is lost from the floating gate 213 to the word gate 205, thereby causing a read disturbance. In FIG. 2B, charge is leaked from the word gate 205 to the floating gate 213, thereby causing a program disturbance. Although read/program disturbance may be prevented by increasing the width of spacer 217, such an approach adversely impacts packing density and restricts further sidewall scaling.
A need therefore exists for flash memory devices exhibiting reduced interference and further sidewall scaling, and for enabling methodology.